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NTE3094 Optoisolator Dual, High Speed, Open Collector NAND Gate
Description: The NTE3094 consists of a pair of inverting optically coupled gates each with a GaAsP emitting diode and a unique integrated detector. The photons are collected in the detector by a photodiode and then amplified by a high gain linear amplifier that drives a Schottky clamped open collector output transistor. each circuit is temperature, current and voltage compensated. This unique isolator design provides maximum DC and AC circuit isolation between input and output while achieving LSTTL/TTL circuit compatibility. The isolator operational parameters are guaranteed from 0 to +70C, such that a minimum input current of 5mA will sink an eight gate fan-out (13mA) at the output with 5 volt VCC applied to the detector. This isolation and coupling is achieved with a typical propagation delay of 57ns. Features: D LSTTL/TTL Compatible: 5V Supply D Ultra High Speed D Low Input Current Required D High Common Mode Rejection D 3000V DC Withstand Test Voltage D Typical Data Rate 10M/Bit(s) Absolute Maximum Ratings: (TA = +25C unless otherwise specified) Input Diode (Each Channel) Reverse Voltage, VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Forward Current, IF Average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Peak ( 1ms Duration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Output Transistor (Each Channel) Supply Voltage (1 Minute Maximum), VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Output Current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16mA Collector Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mW Total Device Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125C Lead Temperature (During Soldering, 1.6mm below seating plane, 10sec Max), TL . . . . . . +260C
Recommended Operating Conditions:
Parameter Input Current, Low Level (Each Channel) Input Current, High Level (Each Channel) Supply Voltage, Output Fan Out (TTL Load) Operating Temperature Symbol IFL IFH VCC N TA Note 1 Test Conditions Min 0 6.3 4.5 - 0 Typ - - - - - Max 250 15 5.5 8 70 C Unit A mA V
Note 1. 6.3mA condition permits at least 20% CTR degradation guardband. Initial switching threshold is 5mA or less. Electrical Characteristics: (TA = 0 to +70C, Note 2 unless otherwise specified)
Parameter High Level Output Current Low Level Output Voltage High Level Supply Current Low Level Supply Current Input-Output Insulation Leakage Current Resistance Capacitance Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance Current Transfer Ratio Resistance (Input-Input) Capacitance (Input-Input) Symbol IOH VOL ICCH ICCL IIO RIO CIO VF V(BR)R CIN CTR RII CII Test Conditions VCC = 5.V, VO = 5.5V, IF = 250A, Note 3 VCC = 5.5V, IF = 5mA, IOL(sinking) = 13mA, Note 3 VCC = 5.V, IF = 0, (Both Channels) VCC = 5.V, IF = 10mA, (Both Channels) Relative Humidity = 45%, TA = +25C, t = 5s, VIO = 3000V DC, Note 4 VIO = 500V, TA = +25C, Note 4 f = 1MHz, TA = +25C, Note 4 IF = 10mA, TA = +25C, Note 3, Note 5 IR = 10A, TA = +25C VF = 0, f = 1MHz, Note 3 IF = 5mA, RL = 100, Note 6 VII = 500V, Note 7 f = 1MHz, Note 7 Min - - - - - - - - 5 - - - - Typ 40 0.4 15 27 - 1012 0.6 1.5 - 60 700 1011 0.27 Max 250 0.6 30 36 1.0 - - 1.75 - - - - - Unit A V mA mA A pF V V pF % pF
Note 2. All typicals at TA = +25C, VCC = 5V unless otherwise specified. Note 3. Each channel. Note 4. Measured between Pin1, Pin2, Pin3 and Pin4 shorted together and Pin5, Pin6, Pin7 and Pin8 shorted together. Note 5. At 10mA, VF decreases with increasing temperature at the rate of 1.6mV/C. Note 6. DC Current Transfer Ratio is defined as the ratio of the output collector current to the forward bias input current times 100%. Note 7. Measured between Pin1 and Pin2 shorted together and Pin3 and Pin4 shorted together.
Switching Characteristics: (TA = +25C, VCC = 5V unless otherwise specified)
Parameter Propagation Delay Time Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) Common Mode Transient Immunity Symbol tPLH tPHL tr tf CMH CML IF = 0mA, VO(min) = 2V IF = 7.5mA, VO(max) = 0.8V VCM = 10VP-P, RL = 350 Test Conditions IF = 7.5mA, RL = 350, CL = 15pF Note 8 Note 9 Min - - - - - - Typ 57 45 25 35 500 -500 Max Unit 75 75 - - - - ns ns ns ns V/s V/s
IF = 7.5mA, RL = 350, CL = 15pF, Note 3
Note 3. Each channel. Note 8. The tPLH propagation delay is measured from the 3.75mA point on the trailing edge of the input pulse to the 1.5V point on the trailing edge of the output pulse. Note 9. The tPHL propagation delay is measured from the 3.75mA point on the leading edge of the input pulse to the 1.5V point on the leading edge of the output pulse. Note10. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dv cm/dt on the leading edge of the common mode pulse (VCM) to assure that the output will remain in a Logic High state (i.e. VO 2.0V). Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dc cm/dt on the trailing edge of the common mode pulse signal (VCM) to assure that the output will remain in a Logic Low state (i.e. VO 0.8V).
Pin Connection Diagram Anode 1 1 2 3 4 8 VCC 7 VO 1 6 VO 2 5 GND
Cathode 1 Cathode 2 Anode 2
8
5
.250 (6.35)
1
4
.390 (9.9) Max .020 (.508) Min Seating Plane .185 (4.7) Max
.100 (2.54)
.115 (2.94) Min

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